FPGA Architecture for the Implementation Of Polynomial Matrix Multiplication

In this paper, the Polynomial Matrix Multiplication (PMM) of polynomial vectors and/or polynomial matrices have been introduced. This method provides an improvement of the fast convolution technique to multiple inputs multiple output systems (MIMO). It is devoted to the hardware implementation of PMM. The hardware implementation of this method is achieved via partly systolic, field programmable gate array (FPGA) with highly pipelined architecture. The architecture, which is flexible in terms of the order of the input polynomial matrices, Xilinx system generator tool has been used for designing. The application to sensor array signal processing strong decorrelation is highlighted. The results are demonstrated to verify the efficient performance of the architecture. The result proved that the proposed solution gives low execution times and the number FPGA resource is less.